Nonvolatile cross-point memory technologies such as Resistance random access memory (ReRAM) and Magnetic random access memory (MRAM) using magnetic tunnel junctions (MTJs) are strong candidates for providing a dense and fast non-volatile storage solution for future memory applications.
A conventional MTJ includes at least a pinned ferromagnetic layer and a free ferromagnetic layer separated from each other by a thin tunnel barrier layer. The free layer has a reversible magnetization direction that can have two stable directions that are parallel or anti-parallel to a fixed magnetization direction of the pinned layer. Resistance of the MTJ depends on the mutual orientation of the magnetizations in the free and pinned layers and can be effectively controlled.
A typical MRAM device includes an array of memory cells, a plurality of parallel word lines extended along columns (or rows) of the memory cells, and a plurality of parallel bit lines extended along rows (or columns) of the memory cells. The word and bit lines overlay each other but spaced from each other in a vertical direction. Each memory cell is located at a cross-point of a word line and a bit line, and typically includes a single MTJ connected in series with a selection metal-oxide-semiconductor (MOS) transistor. The connected in series MTJ and transistor are electrically coupled to the word line at one terminal and to the bit line at the opposite terminal.
FIG. 1 shows a circuit diagram for a magnetic random access memory (MRAM) array according to a prior art disclosed in U.S. patent application publication US 2012/0281465. U.S. patent application publication US 2012/0281465 discloses in detail various methods of writing bits (“0” and “1”) to the memory cells as well as reading and erasing the bits. The disclosure of US 2012/0281465 is hereby incorporated in its entirety by reference.
FIG. 2 shows a cross sectional view of a magnetic memory cell made with perpendicular magnetic materials according to the prior art.
The circuit described by US 2012/0281465 presents a challenge to controlling the addressing of the memory array for writing, reading or erasing due to the fact alternative current paths are possible than those described in the disclosure. This problem is also described in U.S. Pat. Nos. 7,968,419 and 8,227,788, which teach the use of back to back Schottky diodes in a resistance memory array to solve the cross talk problems associated when reading from the array. FIG. 3 is a circuit diagram of a crosspoint resistance non-volatile memory array including resistance variable elements 105 with back to back Schottky diodes (referred to as current controlling elements) 112 according to U.S. Pat. No. 8,227,788. Word and bit conductive lines are indicated at 101 and 119.
US 2012/0281465 describes location of the selection transistors positioned along the perimeter of the array which still requires valuable die area. The use of MOS transistors as a selection element limits the arrangement of the existing MRAM into three-dimensional configuration due to long interconnects to the selection transistor from the remote layers of MTJs. Moreover, the MOS technology is relatively expensive.
An improved method of addressing the word and bit selection transistors in MRAM memory arrays is required that retains the advantages of small die size due to the cross-point design of the memory array and eliminates the MOS transistors altogether to enable lower cost.
The present application addresses the above problems and provides a solution for low cost three-dimensional non-volatile cross-point memory arrays.